China Develops 3 nm Transistors Without EUV Lithography

In a bold stride toward semiconductor self-reliance, China’s IMECAS has demonstrated functional 3 nm-class gate‑all‑around transistors using deep ultraviolet lithography—sidestepping the EUV tools from which it’s barred.

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A Landmark Lab Achievement, Not a Production Node

At the IC World conference in Beijing, Ye Tianchun of IMECAS announced that the institute has completed “early process integration” for stacked‑nanosheet GAA transistors using immersion DUV lithography, bypassing EUV scanners . The devices achieved Ion/Ioff ratios of 9.7 × 10⁵ and 7.6 × 10⁵—well above the 5 × 10⁵ threshold—indicating effective gate control . However, IMECAS has not disclosed key geometric metrics such as gate pitch, metal pitch, nanosheet dimensions, transistor or SRAM density, precluding any direct comparison with commercial 3 nm nodes from TSMC, Samsung, or Intel .

Why DUV Matters—and Its Limits

China remains barred from purchasing cutting‑edge EUV lithography tools, a critical constraint given ASML’s monopoly on such systems . In this context, leveraging immersion DUV and multi‑patterning techniques offers a plausible—but complex—alternative for pushing toward sub‑3 nm features . While the Ion/Ioff performance suggests promising transistor‑level behavior, DUV inherently lacks the resolution of EUV, and scaling to high‑volume manufacturing with acceptable yields remains a steep climb .